Seminars

This page is created to inform any interested participants regarding the seminars to be conducted for the EE690 Graduate Seminars course.  The schedule and the content will be updated throughout the semester.


2023-2024 Spring Graduate Seminars

Seminar Schedule
Date Time Location Speaker Institution & Country Topic
March 4 13:40 D-231 Oğuz Ergin TOBB University of Economics and Technology (ETÜ), Ankara, Türkiye A Potpourri of Ideas and Results in DRAM, FPGA Infrastructures, and RISC-V Processors

Title: A Potpourri of Ideas and Results in DRAM, FPGA Infrastructures, and RISC-V Processors

Abstract: In this talk, I will give an overview of some recent ideas and results in DRAM based random number generation, FPGA based DRAM testing and evaluation infrastructures, undervolting in FPGAs, and RISC-V processor design. This presentation will cover innovative advancements in True Random Number Generators (TRNGs) and FPGA efficiency. Specifically, the talk describes QUAC-TRNG, a high-throughput TRNG that can be implemented in commodity DRAM chips, demonstrating substantial improvements in throughput and utilization compared to state-of-the-art DRAM-based TRNGs. It also introduces DR-STRaNGe, an end-to-end system design addressing the key challenges associated with DRAM-based TRNGs, achieving significant improvements in performance, fairness, and energy consumption. The talk will outline a new experimental infrastructure, DRAM Bender, and briefly discuss the Processing-in-DRAM framework (PiDRAM) to facilitate in-memory processing. The presentation will further explore the effects of undervolting FPGAs on the efficiency and accuracy of convolutional neural network benchmarks, including the surprising impact of temperature and humidity on fault rates. Finally, the ongoing work on utilizing the occurring faults in FPGA undervolting for random number generation (TuRaN) will be discussed, reflecting a broad exploration of cutting-edge techniques in TRNGs, DRAM technology, and FPGA efficiency.
Before we conclude our presentation, we will explain the RISC-V based processor core design efforts in our KASIRGA research group.

Bio: Oguz Ergin is a professor and chair in the department of computer engineering, TOBB ETÜ, Ankara, Turkey. He received his BS degree in electrical engineering from Middle East Technical University in 2000 and MS, PhD degrees from State University of New York at Binghamton in 2003 and 2005 respectively. He was a senior research scientist in Intel Barcelona Research Center during 2004 and 2005. For the last 18 years he has been a faculty member in TOBB ETÜ. He was a visiting associate professor in the University of Notre Dame in 2014, a visiting researcher in University of Edinburgh in 2015-2016 and a visiting professor in ETH Zürich, as part of EFCL and SAFARI in 2023.


 

 

Son Güncelleme:
27/02/2024 - 19:55